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Si5040
9. Pattern Generation and Checking
The Si5040 includes a programmable pattern generator and checker function in both the receiver and transmitter
signal paths. The Si5040 can generate and check PRBS7, PRBS31, or a 64-bit, user-defined pattern programmed
in the tpSel register (receiver Register 29, transmitter Register 157).
Notes:
1. When PRBS7 or PRBS31 is selected for the pattern generator or checker, the pattern can either be inverted or non-
inverted by programming the tpGenInvert and tpChkInvert bits in the pgSel register (receiver Register 29, transmitter
Register 157). Per Section 5.8 in O.150, PRBS31 is specified as an inverted pattern. The pattern generators default to
generating an inverted PRBS31 to comply with 0.150. However, the pattern generators and checkers have the option to
invert the pattern.
2. The pattern checker will report no error if the input sequence is an all 0s pattern. However, a loss-of-lock or loss-of-signal
indicator will assert in these conditions.
The user-defined patterns are programmed in the tpArbGenPtn and tpArbChkPtn registers (receiver Registers 31–
38 and transmitter Registers 159–166). The time period or number of bits over which the checker should look for
errors is defined in the tpTimeBase bits located in the tpChkConfig register (receiver Register 30, transmitter
Register 158). The time base can be programmed to be infinite (always looking for errors) or set to one of three
defined values. Changing to another time base will reset the error counter.
The pattern checker offers a Loss-of-Sync indicator along with a 40-bit error count register and an 8-bit error count
register in floating point notation. When the checker achieves synchronization between the expected and the
received pattern, the tpSyncLos register (receiver Register 9, transmitter Register 137) is deasserted. Note that as
soon as the checker is synchronized, the error count register is reset to 0, and error counting begins. As soon as
the checker loses synchronization in the middle of a measuring window defined by the tpTimeBase register, the
error count register is loaded with all 1s, indicating the maximum error count. In order to differentiate between a
Loss-of-Sync event and a bit error event, the user should monitor both the tpSyncLos register and the error count
register described below.
The tpChkErrCnt register holds the error count from the last completed time base if the checker is in a defined time
base mode; otherwise, in the infinite time base setting, the current running error count is stored. An interrupt is
generated when the number of errors exceeds the value loaded in the 8-bit tpTargetErr register (receiver Register
47, transmitter Register 175). The tpChkErr register holds the error count in an 8-bit floating point format.
In order for the pattern generation/check function to operate correctly, a timing source must be applied. A valid
timing source for the receiver pattern generation/check function can be any of the following:
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A reference clock with the device placed in lock-to-reference mode.
Data applied at the RXDIN inputs from which a recovered clock can be derived.
Data applied at the TD inputs from which a recovered clock can be derived and with the device placed in XFI
loopback mode.
A valid timing source for the transmitter pattern generation/check function can be any of the following:
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?
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34
A reference clock with the device placed in lock-to-reference mode.
Data applied at the TD inputs from which a recovered clock can be derived.
Data applied at the RXDIN inputs from which a recovered clock can be derived and with the device placed in
Looptime mode.
Rev. 1.3
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